Segmented non-volatile memory array with multiple sources having improved source line decode circuitry

ABSTRACT

A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This patent application is a divisional of U.S. patent application Ser.No. 10/174,134, filed on Jun. 17, 2002; which is a divisional of U.S.patent application Ser. No. 08/928,957, filed on Sep. 12, 1997, nowissued as U.S. Pat. No. 6,407,941, which is a continuation of U.S.patent application Ser. No. 08/606,215, filed on Feb. 23, 1996, nowissued as U.S. Pat. No. 5,687,117; the specifications of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor memory systemsand in particular to a segmented non-volatile memory array havingmultiple sources so that blocks of the array can be erased separatelyand having improved source line decode circuitry.

BACKGROUND ART

Non-volatile semiconductor memory systems have become increasinglypopular, including flash memory systems. FIG. 1 is a simplified diagramof the cross-section of a typical flash memory cell 10. Cell 10 is anN-channel device formed in a P-type substrate 12. An N-type drain region14 is formed in substrate 12 as is an N-type source region 16. Sourceregion 16 includes an N-type region 16A formed in the substrate 12having an N+-type region 16B formed inside region 16A so as to form agraded source region 16.

The drain and regions source 14 and 16 are spaced apart from one anotherso as to form a channel region 12A in the substrate intermediate the tworegions. A floating gate 18 is disposed above the channel region 12A anda control gate 20 is disposed above the floating gate 18. The floatinggate is separated from the channel region 12A by a thin (100 Å) gateoxide layer 22. The floating and control gates 18 and 20 are typicallyboth formed from doped poly silicon. The control gate 20 is separatedfrom the floating gate 18 by an interpoly dielectric layer 24. Otherthan being capacitively coupled to other elements of cell 10, thefloating gate 18 is electrically isolated from the rest of the cell.

Table 1 below shows typical conditions for performing program, read anderase operations (two approaches) on flash cell 10. TABLE 1 SOURCE DRAINCONTROL OPERATION (V_(S)) (V_(D)) GATE (V_(G)) READ ground +1.5 volts +5 volts PROGRAM ground   +6 volts +12 volts ERASE 1 +12 volts floatground ERASE 2  +5 volts float −10 volts

If cell 10 is in an erased state, the cell will have a thresholdvoltage, called an erased threshold voltage, which is typicallyapproximately +2 volts. If the cell is in a programmed state, the cellwill have a programmed threshold voltage of typically approximately +6volts. In a read operation, the control-gate-to-source voltage of thecell is +5 volts as can be seen from Table 1, above. The drain 14 willbe connected to a small positive voltage of typically +1.5 volts and thesource 16 is grounded. Thus, if the cell 10 is in a programmed state,the cell will not conduct current in the read operation since thegate-to-source voltage of +5 volts is less than the programmed thresholdvoltage of +6 volts. If the cell is in an erased state, the gate tosource voltage will exceed the erased threshold voltage so that the cellwill conduct current. The presence or absence of cell current in a readoperation is detected by a sense amplifier so that the state of the cellcan be determined.

In order to program the flash cell 10, Table 1 indicates that the source16 is grounded and the drain 14 is connected to +6 volts. The controlgate 20 is connected to a high voltage such as +12 volts. Thecombination of conditions will cause electrons to travel from the source16 towards the drain 14. Some of these electrons will possess sufficientenergy to pass through the gate oxide 22 towards the positive voltage onthe control gate 20. Those electrons, sometimes referred to as hotelectrons, will be deposited on the floating gate 18 and will remainthere until the cell 10 is erased. The presence of electrons on thefloating gate 18 will tend to increase the threshold voltage of thecell, as previously noted.

Table 1 depicts two approaches for erasing a cell. The first approach(Erase 1), a cell is erased by floating the drain 14 and applying alarge positive voltage, such as +12 volts, to the source 16. The controlgate 20 is grounded. This combination causes electrons stored on thefloating gate 18 to pass through the thin gate oxide 22 and to betransferred to the source 16. The physical mechanism for the transfer iscommonly referred to as Fowler Nordheim tunneling.

The above conditions for erasing a cell (Erase 1) have been viewed byothers as disadvantageous in that the large positive voltage (+12 volts)applied to the source region is difficult to implement in an actualmemory system. First, the primary supply voltage V_(CC) in a typicalintegrated circuit memory system is +5 volts and is provided by anexternal power supply such as a battery. Thus, one approach would be toinclude a charge pump on the memory integrated circuit which is alsopowered by the primary supply voltage VCC. However, a typical integratedcircuit memory system may include a million or more cells all or a verylarge group of which will be erased at the same time. Thus, the chargepump circuit must be capable of providing relatively large amounts ofcurrent on the order of 20 to 30 milliamperes. This has been viewed byothers as impractical thus necessitating the use of an a second externalsupply voltage for producing the +12 volts applied to the source region.This would typically preclude battery powered operation where multiplebatteries, such as a +5 volt primary supply battery and a +12 voltsbattery, is not practical.

The application of the relatively high voltage of +12 volts has alsobeen viewed as disadvantageous in that there was believed to be atendency to produce high energy holes (“hot” holes) at the surface ofthe source region 16 near the channel region 12 a. These positivecharges were said to have a tendency to become trapped in the thin gateoxide 20 and eventually migrate to the floating gate and slowlyneutralize any negative charge placed on the floating gate duringprogramming. Thus, over time, the programmed state of the cell may bealtered. Other deleterious effects due to the presence of holes havebeen noted, including the undesired tendency to program non-selectedcells.

The above-described disadvantages of the erase conditions set forth inTable 1 (Erase 1) have been noted in U.S. Pat. No. 5,077,691 entitledFLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION. Thesolution in U.S. Pat. No. 5,077,691 is summarized in Table 1 (Erase 2).A relatively large negative voltage ranging from −10 to −17 volts isapplied to the gate 22 during an erase operation. In addition, theprimary supply voltage V_(CC) of +5 volts (or less) is applied to thesource region 16. The drain region 14 is left floating.

Although the source current remains relatively high, the voltage appliedto the source is sufficiently low that the +5 volt primary supplyvoltage V_(CC) can be used directly or the source voltage may be derivedfrom the primary supply voltage using a series regulator or a resistivedivider in combination with a buffer circuit. In either event, since thesource voltage is equal to or less than the primary supply voltage, thelarge source currents required in erase operations can be providedwithout the use of charge pump circuitry. The high impedance controlgate 20 of the flash cell draws very little current. Accordingly, thelarge negative voltage applied to the control gate 20 in the eraseoperation can be provided by a charge pump circuit. Thus, according toU.S. Pat. No. 5,077,691, only a single external power supply, the +5volt supply for V_(CC), need be used.

In a flash memory system, the flash cells 10 are arranged in a cellarray which typically includes several rows and several columns ofcells. Each of the rows has an associated word line connected to thecontrol gate 20 of the cells 10 located in the row. Each of the columnshas an associate bit line connected to the drain 14 of each cell locatedin the column. The sources 16 of all of the cells of the array areusually connected in common, but as will be explained, the sources maybe separately connected.

FIG. 2A is a simplified plan view of a conventional layout of a pair offlash cells 10A and 10B of a cell array. FIG. 2B is a schematic diagramof cells 10A and 10B of FIG. 2A. As can be seen in FIG. 2B, cells 10Aand 10B have their respective sources connected in common. Typically,the two sources are actually a single source region shared by the twocells 10A and 10B. Cells 10A and 10B are located in a common arraycolumn and in separated rows. The column has an associated bit line BL0which is connected to the drains of cells 10A and 10B. Cell 10A is in arow having an associated word line WL0 connected to its control gate 20and cell 10B is in an adjacent row having its control gate 20 connectedto an associated word line WL1.

The bit lines, including bit line BL0, extend vertically along the arrayand include an underlying diffusion component 26A of doped semiconductormaterial and an overlying metal line component 26B. The metal linecomponent 26B makes electrical contact with the diffusion component 26Aevery two cells 10 by way of contacts 28. The source lines have ahorizontal segment SLD0 which runs generally parallel to the word linesand is made of doped semiconductor material. The source lines also havea vertical segment SLM0 which runs generally parallel to the bit linesand is formed from metal. The horizontal and vertical components SLD0and SLM0 are electrically connected by way of a contact 30 located atthe intersection of the two segments every two rows of the array.

Cell 10A has its control gate 20 connected to horizontal word line WL0,a doped polysilicon line which extends across the array. Cell 10B hasits control gate 20 connected to horizontal word line WL1 which alsoextends across the array. A flash cell (10A, 10B) is formed at theintersection of each of the word lines and bit lines.

FIG. 3A is a simplified plan view of the layout of a relatively smallconventional flash cell array 32 and FIG. 3B is a schematic diagram ofthe FIG. 3A array. Array 32 is comprised of twelve rows, each having anassociated horizontal polysilicon word line WL0-WL11. The array also hastwelve columns, with each column having an associated metal bit lineBL0-BL11. Array 32 also includes four vertical metal source linesSLM0-SLM3 which are connected in common to the six horizontal diffusedsource lines SLD0-SLD5. Each metal source line SLMN is connected to thediffused source lines SLDN every two rows. The metal source lines SLMare spaced every four columns. For example, adjacent metal source linesSLM0 and SLM1 are separated by four bit lines BL0-BL3.

The metal source lines SLM0-SLM3 are electrically connected together bycircuitry (not depicted) external to array 32. Thus, all of the sourcelines of the array are nominally at the same electrical potential.However, the horizontal diffused source lines SLD0-SLD5 have arelatively high resistance, in comparison to the metal source lines.This high resistance can have an adverse impact upon memory operations,particularly programming and reading operations. The use of multiplemetal source lines functions to reduce the overall source lineresistance. However, each metal line occupies a significant amount ofintegrated circuit area so that the use of multiple metal source lineswill increase the die area and thereby effectively increase the cost ofmanufacturing the cell array.

Flash memory systems are typically erased in bulk. That means thateither all or a large part of the array are erased at the same time. Byway of example, the entire array 32 of FIGS. 3A and 3B would be erasedin a single operation. As indicated by Table 1, this can be accomplishedby applying +12 volts to the common source lines SLM0-SLM3, groundingall of the word lines WLN0-WLN11 and floating all of the bit linesBL0-BL11.

There exist conventional memory arrays which provide the capability oferasing less than the entire array. This feature is particularly usefulin many memory applications where it is desirable to retain some datastored in the memory while erasing and then reprogramming other data inthe memory. The capability of erasing less than the entire memory istypically accomplished by electrically isolating the source lines ofindividual blocks of the memory array. A particular block is erased byapplying a high voltage, such as +12 volts (Table 1) to the source lineassociated with the block being erased. The word lines of the block tobe erased are grounded and the bit lines of the block are left floating.As is known, the word lines and source lines of the erase blocks notbeing erased, the deselected erase blocks, are grounded so that thecells in the deselected erase blocks are not erased.

In large memory arrays, there is an increased likelihood that one ormore cells will be defective. There exists various techniques to corrector otherwise compensate for such defective cells so that the memory willcontinue to be functional. However, there are certain cell failuremechanisms that interfere with the operation of the remainder of thememory and thereby effectively prevent proper memory operation. This isespecially true in memory arrays having separate erase blocks where acell failure in one block may prevent proper operation of the remainingerase blocks.

The present invention is particularly applicable to large memory arrayshaving separate erase blocks. The large arrays can contain cells withcertain failure modes which would ordinarily prevent proper operation ofconventional memories, but which do not prevent operation of a memoryusing an array in accordance with the present invention. These and otheradvantages of the present invention will become apparent to thoseskilled in the art upon a reading of the following Detailed Descriptionof the Invention together with the drawings.

SUMMARY OF THE INVENTION

An arrangement of flash memory cells including a plurality of eraseblocks is disclosed. The erase blocks each include flash memory cellsarranged into an array of rows and columns, with the cells in a columnconnected to bit lines common to each erase block and with the cells ina row connected to a common word line. Each of the erase blocks haseither a single common source line or a group of common source lines.

The arrangement further includes a source line decoder circuitcomprising a separate control transistor associated with each of thecommon source lines, with the control transistor having an inputterminal connected to the associated source line and an output terminalconnected to a common global source line and a control terminal forreceiving a control signal that causes the transistor to switch betweena conductive and non-conductive state. When a cell of a selected eraseblock is being read, programmed or erased, the control transistorsassociated with the other or deselected erase blocks are switched to thenon-conductive state so that the associated source line will be at ahigh impedance level. The high impedance level will reduce thepossibility that a defective cell present in one of the deselected eraseblocks will interfere with the operation of the selected erase block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-sectional view of a conventional flashmemory cell.

FIG. 2A is a plan view of the conventional layout of a pair of flashmemory cells.

FIG. 2B is a schematic diagram of the conventional pair of flash memorycells of FIG. 2A.

FIG. 3A is a plan view of the conventional layout of an array of flashmemory cells.

FIG. 3B is a schematic diagram of the memory cell array of FIG. 3A.

FIG. 4 is a plan view of a layout of another embodiment of a segmentedflash memory cell array arrangement.

FIG. 5 is a schematic diagram of showing an equivalent circuit for oneof the erase blocks of the FIG. 4 array arrangement.

FIG. 6 is a schematic diagram showing an equivalent circuit fordetermining the worst case source line resistance for an exemplary cellof the FIG. 4 array arrangement.

FIG. 7 is a schematic diagram of another embodiment of a segmented flashmemory cell array arrangement.

FIG. 8 is a diagram illustrating the layout of a flash memory cell arrayarrangement having eight separate erase blocks and depicting thelocation of the metal source connect lines and the metal source straps.

FIG. 9 is a schematic diagram of one embodiment of an erase sourcedecoder circuit for use with an array having three erase blocks.

FIG. 10 is a schematic diagram of an alternative erase source decodercircuit in accordance with the present invention.

FIG. 11 is a block diagram of a segmented flash array arrangementutilizing negative gate erase techniques.

FIG. 12 is a block diagram of a further embodiment of a segmented flasharray arrangement utilizing negative gate erase techniques.

FIG. 13 is a schematic diagram of one of the X Decoder Stages used inthe array arrangements of FIGS. 11 and 12.

DETAILED DESCRIPTION OF THE INVENTION

Referring again to the drawings, FIG. 4 is a plan view of the layout ofa portion of a segmented flash cell array 34 suitable for use in thepresent invention. Array 34 is comprised of cells 10 as depicted inFIG. 1. A typical array would be much larger than exemplary array 34.The array is divided into rows and columns. The cells 10 located in aparticular row have their control gates all connected to an associatedword line. The cells 10 located in a particular column have their drainregions connected to a particular bit line.

Array 34 includes three erase blocks (sometimes referred to as erasesegments), Blocks 0-2, each of which has separate source lines thatpermit each of the erase blocks to be separately erased. Each eraseblock includes four separate rows of flash cells 10. By way of example,Blocks 0-2 includes four rows associated with word lines WL0-WL3,WL4-WL7 and WL8-WL11, respectively. Further, all of the erase blocksinclude a set of twelve common columns of cells, namely, the twelvecolumns associated with bit lines BL0-BL11. Thus, each of the eraseblocks can be viewed as including an array of flash cells. Bit linesBL0-BL11 are common to all three erase blocks.

Array 34 is fabricated using a single metal layer process so as tosimplify the fabrication process. As is well known, in a single metallayer process, it is not possible for two metal tracks to cross over oneanother. Typically, connections are made in one direction, such as thevertical direction, using metal tracks and in another direction, such asthe horizontal direction, using non-metal tracks, such as dopedsemiconductor tracks.

The erase blocks each include a source line structure which is connectedto all of the source regions of the cells located in the erase blocks.The source line structure includes a plurality of horizontal sourcelines which function to interconnect all of the source regions of cellslocated in one of the rows. The source line structure further includesvertical source lines and source straps which function to interconnectall of the source regions of cells located in one of the columns. Thehorizontal source lines are doped semiconductor source line segmentsintermediate two adjacent word lines. By way of example, Erase Block 2includes a first horizontal doped semiconductor segment SD1 intermediateword lines WL10 and WL11 and a second doped segment SD2 intermediateword lines WL8 and WL9. The two doped source line segments SD1 and SD2of Erase Block 2 extend across the entire width of the array and contactthe common source regions of cells 10 on either side of the source linesegments. Thus, for example, source line segment SD1 of erase Block 2 isconnected to the common source regions of cell 10A and 10B in the rowsassociated with word lines WL11 and WL10, respectively, and to all ofthe other cells located in those rows. Doped source line segment SD2 isconnected to the common source regions in the cell 10 located in the tworows associated with word lines WL8 and WL9.

The two doped source line segments SD1 and SD2 of Erase Block 2 areconnected to a vertical metal source line SL2 by way of contacts 36A and36B. Metal source line SL2 extends over Erase Blocks 0 and 1 and out ofthe array 34 so that the sources of the cells in Erase Block 2 can beconnected to a source line decoder circuit (not depicted) external tothe array 34. Line SL2 does not make contact with either erase Block 0and 1.

FIG. 5 is a schematic diagram showing the series resistances associatedwith the doped source lines SD1 and SD2 of Erase Block 2. Source lineSD1 is represented by series-connected resistors R1A-R15A of equalvalue, with each resistor representing the source line resistancebetween adjacent cell columns. Similarly, resistors R1B-R15B representthe source line resistance of doped source lines SD2. In order to reducethe adverse effects of such resistance, the doped segments areperiodically connected together a fixed number of bit lines by avertical metal track. In the FIG. 4 embodiment, the doped segments SD1and SD2 of erase Block 2 are connected together at one location by metalsource line SL2 intermediate bit lines BL7 and BL8. The diffusedsegments SD1 and SD2 are further connected together at a locationintermediate bit lines BL3 and BL4 by a pair of metal source straps 38Aand 38B. Preferably, the doped source lines are connected together byeither a metal source line or a metal source strap every N number of bitlines, with N being equal to four in the FIG. 4 embodiment. Although twostraps may be used at one location to simplify fabrication, the twostraps are electrically equivalent to a single strap so that the secondstrap may be deleted. Similarly, source strap 38C is positioned adjacentmetal source line SL2 and thus also does not function to reduce theresistance, but is present to simplify the manufacturing process.

As can be seen in FIGS. 4 and 5, each erase block is provided withmultiple source lines. The metal source lines extend out from the array34 and are electrically connected together and to a source line decodercircuit (not depicted) which permits a selected erase block to beerased. As can be seen in FIGS. 4 and 5, Erase Block 2 includes thepreviously-described metal source line SL2 and an edge metal source lineSL2E which is electrically connected to the two doped source lines SD1and SD2 at the edge of array 34. The edge metal source lines SLE2 iselectrically connected to metal source line SL2 outside the array,typically near the source line decoder circuit.

Erase Block 1 (FIG. 4) includes four rows of cells 10 associated withword lines WL4-WL7 and a pair of doped source lines SD3 and SD4. LinesSD3 and SD4 are connected together at one location intermediate bitlines BL3 and BL4 by a metal source line SL1. Metal source line SL1extends over, but does not make electrical contact with, erase Block 0and extends out of the array 34 for connection to the source linedecoder circuitry external to the array 34.

Erase Block 1 further includes a metal source strap 38D located four bitlines over from metal source line SL1 and adjacent to bit line BL0. Afurther metal source strap 38E is located four bit lines away in theopposite direction, intermediate bit lines BL7 and BL8. Another metalsource strap 38F is located another four bit lines away adjacent bitline BL11. Finally, a second metal source line SL1E, located at the edgeof the array, functions to connected the doped source lines SD4 and SD5together and to the source line decoder external to the array.

Erase Block 0 includes a pair of doped source lines SD5 and SD6 whichare associated with four rows of cells 10. Each row has an associatedword line WL0-WL3. Block 0 includes the same twelve columns as arepresent in Blocks 1 and 2 including the columns associated with bitlines BL0-BL11. A first metal source line SL0A is connected to the dopedsource line segments SD5 and SD6 at a location adjacent bit line BL0. Asecond metal source line SLOB located adjacent bit line SL0B is locatedat the other end of the array adjacent bit line BL11. Since the twometal bit lines SL0A and SLOB are located at the opposite ends of thatarray, it is not necessary to provide edge metal source lines, such aslines SL0E and SL1E used in connection with Blocks 0 and 1. Erase Block0 includes a first metal source strap 38F located adjacent bit line BL3and a second metal source line 38G, both interconnecting the diffusedsource lines SD5 and SD6.

As previously noted, the metal lines of the array occupy a significantamount of chip area. Thus, in order to reduce the amount of areaoccupied by the metal source lines and the metal source straps, the twolines and straps are positioned in vertical alignment where possible. Byway of example, metal source line SL1 and metal source strap 38B are inalignment so that the horizontal area occupied is reduced. As a furtherexample, metal source line SL0A and metal source strap 38D are alignedso as to conserve space.

The FIG. 5 diagram of Erase Block 2 illustrates that no cell is morethan two bit lines BLN away from either metal source line going to theoutside (as SL2E or SL2) or a strap (as 38A or 38B). This limits themaximum source line resistance for a worst case cell 10, such as cell10C, to less three time R, where R is equal to the value of any of theindividual source line resistances R1A-R15A. The metal source straps 38interconnecting the doped source lines SD1 and SD2 function to furtherreduce the maximum source line resistance. The metal source straps andthe metal source lines are located such that they alternate a fixednumber of bit lines, such as four bit lines in the FIGS. 4 and 5embodiment.

It can be seen from examination of the FIG. 5 array that cell 10A willhave a source line resistance not greater than the value of equivalentresistor R1A. Other cells 10 of the array will have a greaterresistance, with the overall performance of the array being limited bythe cell with the worst case resistance. FIG. 6 is a schematic diagramof an equivalent circuit of a portion of erase Block 2 of the FIGS. 4and 5 array. Exemplary cell 10C is shown since this cell is located suchthat it is among the cells which will have the largest source lineresistance. Cell 10C is disposed three equivalent resistances (R1A-R3A)away from metal source line SL2E hence the resistor value 3R is shownconnected between the cell and the source line. Cell 10C is furtherdisposed two equivalent resistances (R4A-R5A) away from metal sourcestrap 38A/38B hence the value 2R shown connected to the cell. The strap38A/38B is shown connected to the metal source line SL2 by way ofparallel resistors SR which represent equivalent resistors R6A-R10A andR6B-R10B, respectively. Finally, equivalent resistor SR representingresistors R1B-R5B, is shown connected metal source line SL2E and metalstrap 38A/38B. The two metal source lines SL2E and SL2 are connectedtogether by a line 40 external to array 34.

The total effective resistance between the source of cell 10C and thesource line SL for erase Block 2 can readily be calculated using simplearithmetic. The total effective resistance is equal to parallelcombination of 3R∥(2R+5R/3). This gives an effective approximateequivalent source resistance of 1.6R. If the metal source strap weredeleted, the worst case cell would be cell 10E, with an equivalentsource resistance of approximately 2.5R.

FIG. 7 depicts a portion of another array 42 in suitable for use in thepresent invention. Only a corner portion of the array is depicted,including a portion of an Erase Block 0 and an Erase Block 1. EraseBlock 1 has one metal source line SLN depicted, with there beingadditional metal source lines also associated with Block 1. Erase Block0 has one metal source line SLN+1 depicted, with there being additionalmetal source lines associated with Block 1. Those lines, which extendover Block 0 but do not make contact to Block 0, are also not depictedin that portion of array 42 shown in FIG. 7.

As was the case with the FIG. 4 array, the doped source lines of eacherase block are connected together every four bit lines by either ametal source line or by a metal source strap. By way of example, eraseBlock 0 has two associated doped source lines SDN and SDN+1 which areconnected together by metal straps 38 and source lines SLN+1 every fourbit lines.

In a typical flash cell array, cells located at the edge of the arrayare much more subject to processing variations than the cells notlocated at the edge. Because of this, it is common to refrain from usingthe cells at the array edge. Such cells, which extend around theperimeter of the array, are sometimes referred to as dummy cells. Array42 is surrounded by dummy cells including the two columns of cellsdepicted in FIG. 7 at one edge of the array and two columns not depictedat the opposite edge of the array. The depicted columns are associatedwith bit lines BLX and BLY. In addition, array 42 includes two rows ofdummy cells located at opposite edges of the array, including two rowsnot depicted and two rows shown in FIG. 7. The depicted rows areassociated with word lines WLX and WLY.

The dummy cells have doped source lines which interconnect the sourceregions of the dummy cells. The doped source lines include linesSDZ1-SDZ5 of the two dummy columns and lines SDX and SDY of the twodummy rows. Typically, the bit lines BLX and BLY are not accessed sincethe dummy cells are not supposed to be programmed. If the source linesof the dummy cells, such as source line SDZ5 were to be connected to thesource lines of the array, such as line SDN, the dummy cells would beerased when the array is erased. Since the dummy cells cannot beprogrammed but would otherwise be erased, the dummy cells are likely tobecome overerased so that they will conduct cell current even when theassociated word line is grounded. The flow of current through anovererased cell will usually prevent proper operation of the array. Inorder to ensure proper operation of the array, the doped source lines ofthe dummy rows should not be in electrical contact with the doped sourcelines of the corresponding rows of the functional cells of the array. Byway of example, diffused source line SDN of the rows associated withword lines WLN and WLN+1 does not extend to the diffused source lineSDZ5. In addition, the dummy cells located in the dummy rows would havea tendency to be erased when functional cells located in the same columnare repetitively programmed. This phenomenon is sometimes referred to asbit line disturb where the dummy cells sharing a bit line withfunctioning cells would have some tendency to become overerased and thusbecome leaky. In order to reduce the likelihood of this occurring, thelength of the source lines of the dummy cells are made short so as tominimize the possibility of a leakage path between bit lines. By way ofexample, source lines SDX and SDY of the two dummy rows are notconnected so as to minimize any adverse effects of bit line disturb.

FIG. 8 show a further embodiment of an array 44 in showing essentiallyonly the source line connections. Array 44 is comprised of eight eraseBlocks 0-7, with each of the erase blocks having 128 rows of flashcells. Thus, array 44 has a total of 1024 rows of cells. Array 44 alsohas 1024 columns of cells so that the total array capacity is oneMegabit. Each erase block can be considered an array of cells having 128rows and 1024 columns. As can be seen from FIG. 8, erase Blocks 0-3 anderase Blocks 4-7 are mirror images of one another.

Each of the erase blocks has several vertical metal source lines SLNwhich are electrically connected to all of the horizontal doped sourcelines (not depicted) of the erase block. The metal source lines SLN areprovided a minimum of every 64 bit lines for each erase block, with thevariation being due to the presence of edge metal bit lines. By way ofexample, Erase Block 4 will have 16 metal source lines, including linesSL4A, SL4B, SL4C . . . and SL4O. Each of the erase blocks also includesseveral metal source straps which electrically connect all of thediffused source lines of the erase block together. Erase Block 4includes, for example, metal straps 46A-46I. The metal source straps areinternal to the erase blocks and do not extend past the edges of theassociated erase block. There are typically three metal source strapsintermediate adjacent metal source lines so that there is either a metalsource strap or a metal source line located every 16 bit lines of eacherase block.

The metal source lines SL4A-SL40 of Erase Block 4 extend over EraseBlocks 5-7 and away from array 44 where they are connected together toform a common source line for Erase Block 4. The metal source lines fromBlock 4 extend over the other blocks along a path which is parallel withthe bit lines of the block and orthogonal to the word lines. As will beexplained, the metal source lines from Erase Block 4 (and the othererase blocks) are coupled to a source lined decoder circuit external toarray 44 (not depicted).

Erase Block 5 includes metal source lines SL5A-SL5 which are also spacedapart about every 64 bit lines. The metal source lines of Erase Block 5extend over Erase Blocks 6 and 7 and out of array 44 where they areelectrically connected to the source line decoder. Erase Block 5 alsoincludes metal source straps 48A-48I. The straps, like the straps ofBlock 4, interconnect all of the horizontal doped source lines of Block5. There are typically three metal source straps intermediate adjacentmetal source lines, with there being either a metal source line or ametal source strap every sixteen bit lines.

Erase Blocks 6 and 7 include metal source lines (SL6A-SL6P andSL7A-SL7P, respectively) and metal source straps (50A-50I and 52A-52I,respectively) which are positioned in the same manner as the lines andstraps in Blocks 4 and 5. Note that the location of the metal sourcestraps are selected so that they generally align with the metal sourcelines of adjacent erase blocks. By way of example, metal source straps52B, 50B, and 46B of Erase Blocks 7, 6 and 4, respectively, aregenerally aligned with metal source line SL5B of Block 5. As a furtherexample, metal source straps 46C, 48C and 50D are generally aligned withmetal source line SL7B.

As previously noted, Blocks 0-3 and Blocks 4-7 are arranged so that theyare mirror images of one another. The metal source lines of Blocks 0-3all extend toward the lower edge of array 44 and the metal source linesof Blocks 4-7 all extend in the opposite direction towards the top edgeof the array. By dividing the erase blocks into two groups of blockswith each group of blocks having metal source lines extending in theopposite direction, a reduction in the amount of chip area occupied bythe metal source lines is reduced. By way of example, metal source lineSL3C of Erase Block 3 and metal source line SL4C of Erase Block 4 can bemade to occupy the same vertical path on array 44 since they extend inopposite directions.

FIG. 9 is a schematic diagram of an exemplary section of one embodimentof an erase source decoder circuit 54 which can be used in connectionwith an array having a total of three erase blocks. Circuit 54 includesa set of N channel source line decode transistors 56, 58 and 60connected to the respective source lines of the array. The function ofthe decode transistors is to connect the source lines coming from acommon selected erase block of the array to the same desiredpotential/condition and to connect the source lines from the deselectederase blocks to a desired potential/condition.

By way of example, the source lines from Erase Block 0, includingdepicted lines SL0A and SL0B are connected to decode transistors 56A and56B, respectively. Transistors 56A and 56B, and other decode transistorsnot depicted which are connected to any additional source lines of EraseBlock 0 and have their gates connected to a common line which carriescontrol signal S₀. Source lines from Erase Block 1, including depictedlines SL1A and SL1B, are connected to decode transistors 58A and 58B,respectively. Transistors 58A and 58B, and any other transistors notdepicted which are connected to any additional source lines of EraseBlock 1, have their gates connected to a common line which carriescontrol signal S₁. Erase Block 2 has one source line SL2A depicted inFIG. 9 which is connected to transistor 60. A control line carryingsignal S2 is connected to the gate of transistors 60 and to the gate ofany additional decode transistors which receive other source lines ofErase Block 2. All of the transistors of source decoder circuit 54controlled by control signals S₀, S₁ and S₂ have their source electrodesconnected to a common Global Source line.

Each of the source lines of Erase Blocks 0, 1 and 2 are also connectedto separate N channel transistors 64, 66 and 68 which function toselectively connect the source lines to a common Deselected Source Bus.As will be explained, the Deselected Source Bus may be set to somevoltage or may be grounded. By way of example, transistors 64A and 64Bare connected to source lines SL0A and SL0B of Erase Block 0. The gatesof transistors 64A and 64B are controlled by signal {overscore (S_(o))}which is the complement of signal S₀. Source lines SL1A and SL1B ofErase Block 1 are connected to transistors 66A and 66B, respectively,with transistors 66A and 66B having their gates connected to a commonline which carries signal {overscore (S₁)}, the complement of signal S₁.Transistor 68 is controlled by signal {overscore (S₂)}, the complementof signal S₂, and is connected to source line SL2A of Erase Block 2.

Table 2 below shows the manner in which the source decoder circuit 54 iscontrolled in basic memory operations. In a memory read operation, allof the source lines of all of the erase blocks are to be connected toground. Thus, as can be seen from Table 2, signals S₀, S₁ and S₂ aremade active (connected to voltage V_(CC)) so that transistors 56A, 56B,58A, 56B and 60 are all rendered conductive. The Global Source signal isbrought to ground level so that all of the source lines of the array(SL0, SL1 and SL2) are at ground level. TABLE 2 ERASE SOURCE DECODERREAD PROGRAM ERASE SIGNAL (BLOCK 0) (BLOCK 0) (BLOCK 0) S₀ +5 volts   +5volts   +12 volts S₁ +5 volts   +5 volts      0 volts S₂ +5 volts   +5volts      0 volts {overscore (S₀)} 0 volts 0 volts    0 volts{overscore (S₁)} 0 volts 0 volts +12 volts {overscore (S₂)} 0 volts 0volts +12 volts GLOBAL 0 volts 0 volts +10 volts SOURCE SL0 0 volts 0volts +10 volts SL1 0 volts 0 volts    0 volts SL2 0 volts 0 volts    0volts

Table 3 below shows the conditions for the other portions of the array,including word lines and bit lines, for carrying out memory read,program and erase operations. Although the erase mechanism describedutilizes a grounded gate, negative gate erase could also be used as willbe described. As can be seen from Tables 2 and 3, and as noted above, inmemory read operations, the selected source line (the source lines ofthe erase block containing the cells to be read) are grounded as are thedeselected source lines (the source lines of the other erase blocks).This is accomplished by setting signals S0, S1 and S2 to +5 volts whichcauses transistors 56A, 58A, 60, 56B and 58A to be conductive therebyconnecting all three source lines SL0, SL1 and SL2 to the Global Sourceline. The Global Source line is at ground potential so that all of thesource lines are grounded. Signals {overscore (S₀)}, {overscore (S₁)}and {overscore (S₂)} are all at ground potential during read operationsso that transistors 64A, 66A, 68, 64B and 66B are off. TABLE 3 FUNCTIONREAD PROGRAM ERASE SELECTED +5 volts +11 volts N/A WORD LINE DESELECTED  0 volts    0 volts    0 volts WORD LINE SELECTED BLOCK DESELECTED   0volts    0 volts    0 volts WORD LINE DESELECTED BLOCK SELECTED +1 volt Data = 0 N/A BIT LINE  +6 volts Data = 1    0 volts DESELECTED floatfloat float BIT LINE SELECTED   0 volts    0 volts +10 volts SOURCE LINEDESELECTED   0 volts    0 volts    0 volts SOURCE LINE

In addition, the word line associated with the cells being read (theselected word line) is connected to +5 volts and all of the other wordlines in the array are grounded. The bit lines of the cells being read(eight cells if the memory word length is eight bits) are connected to asmall positive voltage such as +1 volt. All other bit lines of the arrayare left floating, as can also be seen from Table 3. This combination ofconditions will cause the selected cells to either conduct or notconduct current based upon their programmed state.

In order to program a cell (or cells), a relatively large positivevoltage of +11 volts is applied to the word line associated with thecell being programmed. All of the other word lines of the array,including those in the same erase block, are grounded. The bit line ofthe cell to be programmed is connected to +6 volts. If the cell is to beleft in the erased state, the bit line is connected to +1 volt. As shownin Table 3, the deselected bit lines are all left floating duringprogramming operations.

As previously noted, one feature of the present invention is to providean array which contains separate erase blocks which can be independentlyerased. Table 2, above, shows the conditions of the erase source decoderwhen an exemplary erase block, Erase Block 0, is being erased. TheGlobal Source line is set to +10 volts. In addition, signal S₀ is set to+12 volts so that transistors 56A and 56B have sufficient gate voltageto apply the +10 volts present on the Global Source line to the sourcelines SL0A and SL0B associated with the selected erase block, EraseBlock 0. The deselected source lines, those associated with the othererase blocks, are all grounded by setting signals {overscore (S₁)} and{overscore (S₂)} to +12 volts thereby turning on transistors 66A, 68,66B. In addition, the Deselected Source Bus is grounded so that thedeselected source lines SL1A, SL1B and SL2A are all at ground potential.

Table 3, above, shows the conditions of the remainder of the array inerase operations. All of the word lines, including those of the eraseblock being erased and the other erase blocks, are grounded. Inaddition, all of the bit lines of the array are left floating. Underthese conditions, all of the cells in Erase Block 0 will be erased.

Table 3 illustrates one set of conditions for reading, programming anderasing a flash array. In that example, a cell is erased by connectingthe selected source line to +10 volts, the selected word line to groundand floating the selected bit line. As previously noted, negative gateerase techniques could also be used where a negative voltage is appliedto the word line of the cells being erased. That voltage is typically−10 volts to −17 volts as previously described. The bit line is leftfloating and a relatively small voltage V_(A), such as +5 volts, isapplied to the source line of the erase block. As will be explained, thedeselected source lines are left floating rather than being grounded asis done in conventional arrays having separate erase blocks. By floatingthe deselected source lines, certain defects can exist in one eraseblock which do not interfere with the operation of the remaining eraseblocks.

FIG. 10 depicts an alternative source line decoder in accordance withthe present invention. Table 4 below shows the various signals used inthe FIG. 10 decoder, when the decoder is used in connection with anarray utilizing negative gate erase. Referring to FIG. 10, each eraseblock has a separate source line SL0, SL1, SL2 connected to a separatetransistors 70A, 70B and 70C, respectively of the decoder. Transistors70A, 70B and 70C are controlled by signals S₀, S₁ and S₂, respectively.In the event the erase blocks have more than one source line, additionaldecode transistors are included. Thus, for example, if Erase Block 0were to have additional source lines, they would each be connected to atransistor controlled by signal S₀. TABLE 4 ERASE SOURCE DECODER READPROGRAM ERASE SIGNAL (BLOCK 0) (BLOCK 0) (BLOCK 0) S₀ +5 volts   +11volts    +11 volts    S₁ 0 volts 0 volts 0 volts S₂ 0 volts 0 volts 0volts GLOBAL 0 volts 0 volts V_(A) SOURCE SL0 float float V_(A) SL1float float float SL2 0 volts 0 volts float

As can be seen from Table 4, when cells in Erase Block 0 are to be read,signal S₀ is set to +5 volts thereby turning on transistor 70A (and anyother transistors that may be connected to a source line of Erase Block0). Signals S₁ and S₂ remain at ground level so that the transistorsconnected to the remaining erase blocks, including transistors 70B and70A, are left off. Thus, the source lines of all of the deselected eraseblocks are floating. Conducting transistor 70A will connect the sourceline SL0 of Erase Block 0 to the Global Source line which is, in turn,connected to ground. A positive voltage of +5 volts is connected to theword line associated with the cells being read and the bit lines areconnected to a small positive voltage of typically +1 volts. This willcause current to flow or not to flow in the cells being read dependingupon whether the cells are in an erased or programmed state. Table 3,above, shows the conditions for the deselected word lines and bit linesduring read operations.

In a programming operation where cells in Erase Block 0 are to beprogrammed, Table 4 indicates that transistor 70A is turned on andtransistors 70B and 70C are left off. The Global Source line is set toground potential so that transistor 70A will cause the source line SL0to be at ground potential. The deselected source lines SL1 and SL2 willbe floating. The word line associated with the cells being programmed isset to a relatively large positive voltage of typically +11 volts. Sincethis voltage (+11 volts) is generated for programming, the voltage isavailable for generating signal S₀ used to on transistor 70A. Signal S₀could also be +5 volts since transistor 70A is switching at a voltagenear ground potential. Further, the bit line associated with the cellsto be programmed will be set to a medium level voltage such as +6 volts.If the cell is to be left in the erased state, the associated bit lineis grounded. This combination of conditions will permit the selectedcells of Erase Block 0 to be programmed.

Continuing, Table 4 indicates that all the cells of Erase Block 0 areerased by setting signals S₀, S₁ and S₂ such that transistor 70A of theFIG. 10 erase decoder is made conductive and the remaining transistors70B and 70A are off. The Global Source line is set to a relatively lowpositive voltage V_(A) which is typically approximately +5 volts or someother value which will not be so large as to result in cell voltagebreak down. Thus, source line SL0 of Erase Block 0 will be at voltageV_(A) and the source lines of the remaining erase blocks, lines SL1 andSL2 will be floating. The word lines of Erase Block 0 are all set to arelatively large negative voltage, such as −10 volts, and the bit linesof the array are all left floating. This will result in all of the cellsof Erase Block 0 being erased by way of the previously-describednegative gate erase technique.

It is possible that a failure of a cell in one erase block willadversely affect operation of the remaining erase blocks. Under certainconditions, a flash cell will conduct current when it should benon-conducting. By way of example, if a cell has been over erased, thecell will have a negative threshold voltage so that the cell willconduct even when the gate-source voltage is 0 volts. Other conditionsmay occur which will cause a cell to be “leaky” and conduct current whenthe cell should be non-conductive. When a cell of a deselected eraseblock is improperly conducting current, the cell has a tendency to clampthe bit line voltage to the source voltage. This can cause the bit linevoltage to approach ground potential should the source lines of thedeselected erase blocks be set to ground potential as is illustrated inTables 2 and 3, above. Since the bit lines are common to all of theerase blocks in an array, a defective cell in one block will have atendency to interfere with the reading, programming and erasure of theother blocks. By floating the source lines of deselected erase blocksduring program or read, as shown in Table 4, the adverse effects of aleaky or over erased cell in the deselected blocks on the cells ofselected erase blocks will be greatly reduced.

FIG. 11 depicts a flash cell array arrangement using word line controlcircuitry for carrying out negative gate erase. Exemplary Erase Blocks0-1 are depicted, with there being a total of eight erase blocks,including Erase Blocks 2-7 which are not shown. Each erase block hassixty-four word lines WL, a set of bit lines BL common to all of theerase blocks and separate source lines (not depicted). The word linesare grouped in eights, with each group of eight being connected to aseparate X Decoder Stage 72. The functionality provided by X DecoderStages 72 is conventional. By way of example, FIG. 6 of the previouslynoted U.S. Pat. No. 5,077,091 discloses a decoder stage which providesthe same output signals as provided by X Decoder Stages 72. Exemplary XDecoder Stage 72A is connected to word lines WL0-WL7. There are a totalof 512 word lines WL0-WL511, with word lines WL0-WL63 being associatedwith Erase Block 0 and word lines WL64-WL127 being associated with EraseBlock 1 and the remaining word lines WL12B-WL511 being associated withthe remaining six erase blocks that are not depicted.

Each of the word lines WL0-WL511 also has a separate respective Pchannel erase transistor T0-T511 connected to it, with the transistorsassociated with one of the erase blocks being controlled by a commoncontrol signal. Thus, erase transistors T0-T63 of Erase Block 0 havetheir gates connected to a line that carries control signal G0 and erasetransistors T64-T127 of Erase Block 1 have their gates connected to acommon line that carries control signal G1. In addition, all of theerase transistors associated with an erase block have their sourcesconnected to a common voltage line. Thus, for example, erase transistorsT0-T63 are all have their sources connected to a common line thatcarries a voltage V₀.

The details of the X Decoder Stages 72 of FIG. 11 are shown in FIG. 13.As will be explained in greater detail, the X Decoder Stages 72 provideoutputs which are either at a positive voltage equal to the X DecoderStage 72 supply voltage V_(P), ground potential or a high impedance (atleast more than 10 k Ω). The high impedance state of the X DecoderStages 72 is used when the erase transistors T0-T511 function to apply anegative voltage to the word lines of an erase block during an eraseoperation, as will be explained in greater detail.

The conditions for carrying out read, program and erase operations onthe FIG. 11 array arrangement are set forth in Table 5, below. TABLE 5FUNCTION READ PROGRAM ERASE G₀ +5 volts +11 volts −12 volts V₀ +5 volts+11 volts −10 volts G₁ +5 volts +11 volts    0 volts V₁ +5 volts +11volts    0 volts X-DECODER +5 volts +11 volts    0 volts SUPPLY V_(P)WL-BLOCK 0 selected selected −10 volts (SELECTED +5 volts +11 voltsBLOCK) deselected deselected   0 volts    0 volts WL-BLOCK 1   0 volts   0 volts 0 − V_(T) (DESELECTED BLOCKS) SL0   0 volts    0 volts V_(A)SL1   0 volts    0 volts V_(B) (DESELECTED float float float SOURCES)V_(NISO) −2 volts  −2 volts    0 voltsErase Block 0 is the selected erase block in the Table 5 example. As canbe seen from Table 5, if a memory read operation is to occur in EraseBlock 0, all of the control signals connected to the gates of the Pchannel erase transistors T0-T127 (and the erase transistors T128-T511not depicted) are connected to a positive voltage of +5 volts. Thatincludes signal G₀ associated with the selected Erase Block 0 and signalG1 associated with the deselected Erase Block 1. In addition, thevoltages V₀ and V₁ applied to the drains of the P channel erasetransistors are all set to +5 volts. The positive voltages applied tothe erase transistors causes the transistors to be non-conductive.Accordingly, the state of the word lines will be determined by the XDecoder Stages 72 during memory read operations.

Referring again to FIG. 13, further details of the X Decoder Stage 72will now be described. The entire X Decoder, which is not depicted,functions to receive nine of the sixteen address bits for the array anddecodes those address bits so as to select one of the 512 word lines inmemory read and programming operations. The remaining address bits forthe memory are used by a Y Decoder (not depicted) to select theappropriate bit lines. X Decoder Stages 72 represent the output portionof the X Decoder for the array. Each X Decoder Stage 72 is associatedwith eight word lines so that there will be a total of sixty-four XDecoder Stages 72, with eight X Decoder Stages 72 being associated witheach of the eight erase blocks. The exemplary FIG. 13 circuitry for XDecoder Stage 72A is associated with eight word lines WL0-WL7 of EraseBlock 0.

In order to select one of the 512 word lines, each of the X DecoderStages 72 receives a total of twenty-four predecode signals. Thesepredecode signals are developed by predecoding circuitry (not depicted)which receives the nine address bits supplied to the X Decoder andconverts the nine address bits to twenty-four predecode signals,including signals X_(A0)-X_(A7), X_(B0)-X_(B7) and X_(CH0)-X_(CH7).Signals X_(A0)-X_(A7) and X_(B0)-X_(B7), are used in combinations of twoto select one of the sixty-four X Decoder Stages 72. SignalsX_(CH0)-X_(CH7) are provided to each of the sixty-four X Decode Stages72 to select one of the eight word lines associated with each stage. Byway of example, X Decode Stage 72A of FIG. 13 receives predecode signalsX_(A0) and X_(B0) which function to select that stage from thesixty-four stages. Stage 72A also receives predecode signalsX_(CH0)-X_(CH7) which are used to select one of the eight word linesWL0-WL7 associated with Stage 72A.

The construction and operation of exemplary X Decode Stage 72A of FIG.13 will now be described since such description is helpful inunderstanding Table 5. Predecode signals X_(A0) and X_(B0) are connectedto the inputs of a NAND gate 74, the output of which is connected to alevel shifting pass transistor 76 which will pass any voltage having amagnitude which is below the supply voltage V_(CC) connected to itsgate. Pass transistor 76 is, in turn, connected to a total of eightadditional pass transistors, including N-channel transistor 78Aassociated with decode circuitry for word line WL0 and including Nchannel transistor 78B associated with decode circuitry for word lineWL7.

Transistor 78A has its gate connected to receive predecode signalX_(CH0), with predecode signal X_(CH0) also being connected to the gateof a P channel transistor 80A. Transistor 80A is connected betweentransistor 78A and the X Decoder supply voltage V_(P). Transistors 78Aand 80A are connected to a common node 79A which is near groundpotential when predecode signals X_(A0), X_(B0) and X_(CH0) are all at ahigh level, otherwise node 79A is at a high level. Node 79A is connectedto the common gate connection of a P channel transistor 84A and an Nchannel transistor 88A. These transistors form an inverting stage, theoutput of which is connected to word line WL0. Transistor 84A isconnected between the X Decoder supply voltage V_(P) and the invertingstage output and transistor 88A is connected between the output, by wayof a P channel transistor 86A, and the circuit common. As will beexplained, transistor 86A functions to protect N channel transistor 88Afrom the negative voltage which is present on the word line WL0 duringerase operations.

In addition to being connected to word line WL0, the output of theinverting stage is connected to the gate of a feedback P channeltransistor 82A, with transistor 82A providing positive feedback whichpulls the input of the inverting stage, node 79A, towards supply voltageV_(P) when the output of the inverting stage, WL0, goes low. Thisensures that node 79A will be pulled up to a sufficiently high voltageto turn off P channel transistor 84A.

The remaining seven sections (only the last section is depicted) of XDecoder Stage 72A for driving word lines WL1-WL7 are also connected tothe output of NAND gate 74 and pass transistor 76. Otherwise, theconstruction of the sections is the same. The seven sections eachreceive respective ones of predecode signals X_(CH1)-X_(CH7), so thatone of the eight word lines WL0-WL7 can be selected.

Returning to the description of a read operation (Table 5 and FIG. 11)in connection with Erase Block 0, the signals G₀-G₇ applied to the gatesof all of the P channel erase transistors T0-T127 (and those notdepicted) are set to +5 volts. Thus, the transistors will benon-conductive. In addition, the X Decoder supply voltage V_(P) is setto +5 volts. A read address is decoded causing predetermined predecodesignals to become active. Assuming, for example, that a cell associatedwith word line WL7 is to be read, the predecode signals X_(A0) andX_(B0) will go high thereby selecting X Decoder Stage 72A. This willcause the output of pass transistor 76 to go low (FIG. 13). In addition,predecode signal X_(CH7) Will go high thereby turning on pass transistor78B and causing node 79B to go low. The remaining predecode signals,X_(CH0)-X_(CH6) will remain low. Transistor 84B will turn on so as topull up selected word line WL7 to voltage V_(P), which is set to +5volts. Note that voltage V_(NISO) is set to −2 volts (Table 5) therebycausing P channel transistor 86B to be conductive. However, sincetransistor 88B is off, the word line WL7 voltage will still be +5 volts.

As indicated in Table 5, the deselected word lines in the selected EraseBlock 0 are set to ground potential. This is accomplished by the ninebit address causing the X Decoder to set the predecode signalsX_(CH0)-X_(CH6) to a low value, as previously noted. Thus, for example,signal X_(CH0) will cause transistor 78A to turn off thereby isolatingnode 79A from the low output of NAND gate 74. Signal X_(CH0) will alsocause transistor 78A to become conductive and pull node 79A up tovoltage V_(CC) less the threshold voltage of transistor 79A. This willcause transistor 88A to become conductive, thereby causing the voltageon word line WL0 to drop. This, in turn, will cause transistor 82A toturn on thereby pulling node 79A up further to voltage V_(P). Aspreviously noted, voltage V_(NISO) is set to −2 volts so that transistor86A will also be conductive. Accordingly, transistors 86A and 86B willboth be conductive and will pull word line WL0 down to ground potentialas will the corresponding transistors associated with deselected wordlines WL1-WL6 of Erase Block 0.

With respect to the deselected word lines of the remaining erase blocks,Table 5 indicates that these word lines are also set to groundpotential. For all of these deselected erase blocks, the predecodesignals XA and XB will such that the output of the corresponding NANDgate 74 output will be at a high level. For those deselected word lineswhere predecode signal X_(CH7) is used, that predecode will be at a highlevel in the present example so that transistor 78 will be on therebyconnecting the high output of NAND gate 74 to node 79. For thoseselected word lines where predecode signals X_(CH0)-X_(CH6) are used,those predecodes will be at a low level. This will cause the associatedtransistor 78 to be off thereby isolating node 79 from the output of theNAND gate 74. In addition, associated transistor 80 will be turned on bythe low level predecode so that node 79 will be pulled up to voltageV_(P). In either case, a high voltage at node 79 will cause theassociated word line to be at ground potential.

As indicated by Table 5, in read operations, the selected source line,SL0 for Erase Block 0, is grounded. The source lines of the remainingErase Blocks 1-7, including source line SL1, can also be grounded asshown in Table 5. However, it is an objective of the present inventionto cause the deselected source lines to be left floating, as also shownin Table 4. This can be accomplished, for example, using the sourcedecoder circuit of FIG. 9. With the array configured as described, aselected cell (or group of cells) associated with a word line (such asline WL7) of Erase Block 0 can be read.

Table 5 also shows the conditions for programming a cell or group ofcells of the FIG. 11 array arrangement. Again, all of the P channelerase transistors T0-T511 are turned off since control signals G₀ and G₁(and signals G₂-G₇ not depicted) are all set to a positive voltage (+11volts). The X Decoder 72 supply voltage V₂ is set to +11 volts and thedecoding circuitry is caused to apply this voltage to the selected wordline based upon the address being used in the programming operation.Thus, for example, if word line WL7 is the selected word line, predecodesignals X_(A0), X_(B0) and X_(CH7) (FIG. 13) are all at a high level sothat transistor 84B will pull word line WL7 up to voltage V_(P) set to+11 volts.

The deselected word lines WL0-WL6 of selected Erase Block 0 are set toground potential in the programming operation since the predecodesignals X_(CH0)-X_(CH6) associated with the deselected word lines willbe at a low level. Voltage V_(NISO) is set to −2 volts according toTable 5 therefore both transistors 86B and 88B will be turned onconnecting these deselected word lines to ground as was the case duringread operations. In addition, the word lines of the deselected eraseblocks will be at ground potential for the same reasons previously setforth in connection with the description of an exemplary read operation.However, it is again an object of the present invention to have thesource line of the deselected erase blocks be left floating inprogramming operations as is the case of these source lines during readoperations.

In erase operation, a single erase block of the array may be erased aspreviously described. As can be seen in Table 5, if Erase Block 0 is theselected block to be erased, signal G₀ is set to −12 volts therebyturning on erase transistors T0-T63 (FIG. 12). In addition, voltage V₀is set to −10 volts so that all sixty-four word lines of Erase Block 0are connected to −10 volts by the associated erase transistor T0-T63.

As can also be seen from Table 5, all sixty-four of the X Decoder Stages72 of the array have their common supply voltage V_(P) set to groundpotential. In addition, voltage V_(NISO) is set to ground potential sothat the P channel transistor 86 (FIG. 13) in each of the X DecoderStages 72 is turned off thereby isolating the N channel transistors 88from the negative voltage which is applied to the word lines of SelectedErase Block 0.

The erase transistors T64-T511 of the deselected erase blocks are allturned off since the voltage applied to the gates, including G₁, is atground potential. In addition, the associated X Decoder Stage 72 outputis isolated from the word lines so that the word lines of the deselectederase blocks will be at a high impedance level. The deselected wordlines will assume a voltage ranging from ground potential to thethreshold voltage V_(T) of the P channel transistor 84 located in theassociated X Decoder Stage 72, as indicated in Table 5. This thresholdvoltage is typically +1 volt.

The source line of the selected Erase Block 0, source line SL0, is setto voltage V_(A) which is typically +5 volts. By way of example, theGlobal Source line of the FIG. 9 source decoder circuit will be set tovoltage V_(a) and signal S0 is made to turn on transistors 56A and 56B.In addition, the voltage of the source lines associated with thedeselected erase blocks, such as source line SL1, are set to a voltageV_(B). This is accomplished by setting the Deselected Source Bus of theFIG. 9 decoder circuit to voltage V_(B) and turning on the transistors66A, 66B and 68 associated with the selected source lines. Voltage V_(B)is selected to be intermediate threshold voltage V_(T) and voltage V_(A)applied to the selected source line. Thus, if threshold voltage V_(T) is+1 volt and voltage V_(A) is +5 volts, VB may be set to +3 volts. Ifvoltage V_(B) is set too high, there will be an increased tendency forthe cells of the deselected erase blocks to be slightly erased each timeone of the other erase blocks is erased. This phenomena is sometimesreferred to as source erase disturb. If, on the other hand, voltage VBis too low, there will be a tendency to turn on the deselected flashcells, or to cause them to leak, since the control gate voltage of theflash cells will typically be at voltage V_(T) due to the previouslydescribed influence of the associated X Decoder Stage 72. Theseconditions will cause the selected Erase Block 0 to become erased. Asalso indicated by Table 5, the deselected course lines can also beplaced in a floating state in erase operations.

FIG. 12 shows an alternative embodiment of an array arrangement for usein the subject invention. Those elements of the alternative embodimentthat are similar to the FIG. 11 embodiment have the same numericaldesignation. This array arrangement also utilizes negative gate eraseduring erase operations. However, rather than having a separate controlsignal G₀-G₇ for each of the eight Erase Blocks 0-7, there is singlecontrol signal G common to all eight blocks. Other aspects of the FIG.12 embodiment are the same as that of FIG. 111 with the exception of thedifferences noted in the following description. Thus, the FIG. 12 arrayarrangement is somewhat simpler to implement than is the FIG. 11embodiment.

Table 6 shows the conditions for reading, programming and erasing theFIG. 12 array arrangement. In read operations, signal G is set to +5volts so that all of the erase transistors T0-T511 are turned off.Similarly, in program operations, signal G is set to +11 volts so thatall of the erase transistors are turned off. The X Decoders stages 72used in the FIG. 12 embodiment are the same used in the previouslydescribed FIG. 11 embodiment. Since the erase transistors T0-T511 are inthe same corresponding disabled state as in the FIG. 11 embodiment, theconditions created by the X Decoder Stages 72 in read and programoperations are the same and need not be further described. TABLE 6FUNCTION READ PROGRAM ERASE G +5 volts +11 volts −12 volts V₀ +5 volts+11 volts −10 volts V₁ +5 volts +11 volts    0 volts X-DECODER +5 volts+11 volts    0 volts SUPPLY V_(P) WL-BLOCK 0 selected selected −10 volts(SELECTED +5 volts +11 volts BLOCK) deselected deselected   0 volts    0volts WL-BLOCK 1   0 volts    0 volts    0 volts (DESELECTED BLOCKS) SL0  0 volts    0 volts V_(A) SL1   0 volts    0 volts V_(B) (DESELECTEDfloat float float SOURCES) V_(NISO) −2 volts  −2 volts    0 volts

In erase operations, assume that Erase Block 0 is to be erased. Commonsignal G is set to −12 volts and voltage V₀ associated with Erase Block0 is set to −10 volts. Thus, erase transistors T0-T63 are turned onthereby connecting all of the word lines WL0-WL63 of Erase Block 0 to−10 volts. The deselected voltages, including V₁ are all set to groundpotential. Thus, the remaining erase transistors T63-T511 are all turnedon thereby connecting all of the deselected word lines WL64-WL511 toground.

As also indicated by Table 6, the selected source line SL0 is set tovoltage V_(A) which, as previously noted, is typically +5 volts. Thedeselected source lines, including source line S1, are connected tovoltage V_(B) which, as also previously noted, is set to +3 volts, avoltage selected to be greater than the threshold voltage of the XDecoder Stage 72 P channel transistor 86 (FIG. 13) and lower thanvoltage V_(A). Again, voltage V_(NISO) is set to 0 volts thereby turningoff transistor 86 of the X Decoder Stages 72 and isolating the N channeltransistors 88 from the negative voltage applied to the word linesWL0-WL63 of Erase Block 0. Although not set forth in Table 6, the bitlines common to all of the erase blocks are left floating. Thiscombination of conditions will cause the cells of Erase Block 0 to beerased.

As indicated by Table 6, in erase operations, the deselected sourcelines can also be left floating. This approach is preferred since, aspreviously noted, a defect is a deselected erase block will notadversely affect the operation of the selected erase block.

Thus, a novel flash cell array arrangement divided into array segmentshaving separate source lines and associated source line decode circuitryhas been disclosed. Although a various embodiments of the subjectinvention have been described in some detail, it is to be understoodthat certain changes can be made by those skilled in the art withoutdeparting from the spirit and scope of the invention as defined by theappended claims.

1. A method comprising: forming a plurality of memory cells, the memorycells including a number of sources, each of the sources correspondingto a source of one of the memory cells; forming a plurality of firstsource lines coupled to the number of sources; forming a plurality ofsecond source lines coupled to the first source lines, the memory cellsarranged in a plurality of columns, wherein the second source lines arespaced apart by a first number of columns of the plurality of columns;and forming a plurality of source line straps coupled to the firstsource lines, wherein the source line straps are spaced apart by asecond number of columns of the plurality of columns.
 2. The method ofclaim 1, wherein the first source lines are formed from semiconductormaterial.
 3. The method of claim 2, wherein the second source lines areformed from conductive material.
 4. The method of claim 3, wherein thesource line straps are formed from conductive material.
 5. The method ofclaim 1, wherein the first source lines and the second source lines areorthogonal.
 6. The method of claim 1, wherein the first and secondsource lines are parallel.
 7. The method of claim 1, wherein the firstnumber of columns of the plurality of columns is greater than the secondnumber of columns of the plurality of columns.
 8. A method comprising:forming a first row of memory cells, the memory cells including a numberof sources, each of the sources corresponding to a source of one of thememory cells; forming a second row of memory cells, the memory cells ofthe second row including a number of sources, each of the sourcescorresponding to a source of one of the memory cells, wherein memorycells of the first and second rows are arranged in a plurality ofcolumns; coupling the sources of the memory cells of the first rowtogether using a first source line; coupling the sources of the memorycells of the second row together using a second source line; couplingthe first source line to the second source using a conductive sourceline; and coupling the first source line to the second source using aplurality of source line straps, wherein the source line straps arespaced apart by a number of columns of the plurality of columns.
 9. Themethod of claim 8, wherein the first and second source lines are formedfrom semiconductor material.
 10. The method of claim 8, wherein theconductive source line is formed from a material in which the materialincludes metal.
 11. The method of claim 8, wherein the source linestraps are formed from a material in which the material includes metal.12. The method of claim 8, wherein the number of columns of theplurality of columns is four.
 13. The method of claim 8, wherein thefirst and second source lines are parallel.
 14. The method of claim 13,wherein the first and second source lines are orthogonal to the sourceline straps.
 15. The method of claim 14, wherein the conductive sourceline is parallel with the source line straps.
 16. A method comprising:fabricating a plurality of horizontal source lines in a memory array,each of the horizontal source lines having a resistance per unit length;connecting the horizontal source lines together using a vertical sourceline; connecting the horizontal source lines together at a plurality ofhorizontal locations using a plurality of vertical source line straps;and connecting the vertical source line to a global source line througha first plurality of switches.
 17. The method of claim 16 furthercomprising: connecting the vertical source line to a source bus througha second plurality of switches.
 18. The method of claim 16, wherein thehorizontal source lines include semiconductor material.
 19. The methodof claim 16, wherein the horizontal source lines includes dopedpolysilicon.
 20. The method of claim 19, wherein the vertical sourceline includes metal.
 21. The method of claim 16, wherein the verticalsource line includes a material different from a material of thehorizontal source lines.
 22. A method comprising: fabricating a firstrow of flash memory cells, the flash memory cells including a number ofsources, each of the sources corresponding to a source of one of theflash memory cells; fabricating second row of flash memory cells, theflash memory cells of the second row including a number of sources, eachof the sources corresponding to a source of one of the flash memorycells, wherein the flash memory cells of the first row and the secondrow are arranged in a plurality of columns; coupling the sources of theflash memory cells of the first row together using a first source line;coupling the sources of the flash memory cells of the second rowtogether using a second source line; coupling the first source line tothe second source using a plurality of conductive source lines, whereinthe conductive source lines are spaced apart by a first number ofcolumns of the plurality of columns; and coupling the first source lineto the second source using a plurality of source line straps, whereinthe source line straps are spaced apart by a second number of columns ofthe plurality of columns.
 23. The method of claim 22, wherein the firstand second source lines are formed from doped semiconductor material.24. The method of claim 23, wherein the source lines are formed from amaterial in which the material includes metal.
 25. The method of claim24, wherein the source line straps are formed from a material in whichthe material includes metal.
 26. The method of claim 22, wherein thefirst number of columns of the plurality of columns is sixteen.
 27. Themethod of claim 26, wherein the second number of columns of theplurality of columns is four.
 28. The method of claim 22, wherein thefirst and second source lines are parallel.
 29. The method of claim 28,wherein the first and second source lines are orthogonal to theconductive source.
 30. The method of claim 29, wherein the conductivesource lines and the source line straps are parallel.
 31. The method ofclaim 22 further comprising: forming a number of first switches tocouple the conductive source lines to a global source line.
 32. Themethod of claim 31 further comprising: forming a number of secondswitches to couple the conductive source lines to a source bus.
 33. Amethod comprising: forming a first block of flash memory cells and asecond block of flash memory cells, each of the first and second blocksincluding a number of sources, each of the sources corresponding to asource of one of the flash memory cells; forming in each of the firstand second blocks a plurality of first source lines coupled to thenumber of the sources; forming in each of the first and second blocks anumber of second source lines coupled to the plurality of first sourcelines; and forming in each of the first and second blocks a number ofsource line straps coupled to the first source lines.
 34. The method ofclaim 33, wherein the second source lines of the first block extend overthe second block.
 35. The method of claim 34, wherein a length of eachof the source line straps of the first block remains within the firstblock, and wherein a length of each of the source line straps of thesecond block remains within the second block.
 36. The method of claim33, wherein the flash memory cells of the first and second blocks arearranged in a plurality of rows and a plurality of columns, wherein thesecond source lines of each of the first and second blocks are spacedapart by a first number of columns of the plurality of columns, andwherein the source line straps of each of the first and second blocksare spaced apart by a second number of columns of the plurality ofcolumns.